1) Field of the Invention
The invention is in the field of Semiconductor Devices.
2) Description of Related Art
For the past decade, the performance of semiconductor devices, such as Metal Oxide Semiconductor Field-Effect Transistors (MOS-FETs), has been greatly enhanced by the incorporation of metallized regions into the active portions of a semiconductor substrate, e.g. the self-aligned silicide (SALICIDE) process. The presence of such a metallized region greatly reduces the external resistance at the junction of a metal contact, extending from an array of metal interconnects, and a source/drain region.
FIG. 1 depicts a typical MOS-FET 100, wherein a substrate is comprised of an isolation region 101 and an active region 102. A gate dielectric layer 103 sits above active region 102 and a gate electrode 104 sits above gate dielectric layer 103. Gate dielectric layer 103 and gate electrode 104 are isolated by gate isolation spacer 106. Tip extensions 105 and source/drain regions 107 are formed by implanting dopant atoms into active region 102. A portion of active region 102 is amorphized to form amorphized region 108. Amorphized region 108 can suppress metal pipe formation during a metallization process to form, for example, metallized regions 110A and 110B.
When the SALICIDE or metallization process metallizes the amorphous region 108 at both a top surface 112 and a sidewall 113 of active region 102 to form metallized regions 110A and 110B, metal pipe defect 115 may form and short the MOS-FET device by extending from one source/drain region 107 to another source/drain region. The formation of such a metal pipe defect can render a semiconductor device non-functional. In some cases, an extensive amorphized region is formed to suppress metal pipe defect formation. The amorphization process, however, can degrade MOS-FET performance as a result of a poor quality junction between the source/drain region and the active region. Another approach involves reducing the duration and frequency of cleans steps used during formation of a semiconductor device, in order to mitigate the extent of the recess of top surface 111 of the isolation region 101 relative to top surface 112 of the active region 102. When top surface 111 is below top surface 112, sidewall 113 of active region 102 is exposed, forming a pathway for metal pipe formation during the SALICIDE or metallization step, as described above. A reduced recess may be favorable for hindering metal pipe formation, but reducing or eliminating cleans steps can have detrimental manufacturing consequences, such as lower yield due to residue or particle defects. Thus, a method to suppress the formation of metal pipe defects in semiconductor devices is described herein.